Vulcan THE HARDWARE FORGE
GitHub

AI-assisted hardware engineering

Hardware,forged anew.

Plan the architecture, implement the design, and verify the results with Vulcan.

Enter the workshop Discover the designs

FROM THE MOUNTAIN. INTO THE WORKSHOP.

The fire is lit.The tools are ready.

Draw the blueprint, write the code, and check each part with tests.

OPEN RTL. REAL RESULTS.SCROLL INTO THE FORGEVULCAN / 0.1
01THE ORIGIN
NOTES FROM THE FORGE

START WITH A DESIGN QUESTION.

Bring AI into
hardware development.

Vulcan brings planning, implementation, verification, and independent review into one workflow, with a focus on digital AI accelerators.

Heat. Shape. Test. Refine.CHECK THE WORK AS YOU GO.

ON THE WORKBENCH
TONGS / HAMMER / CALIPERSEach tool has a job to do.
I.Designs you can explore.

Explore released SystemVerilog for buffers, DMA, packet routing and shared memory access.

II.Results with clear scope.

Each featured design presents its capabilities and measured verification highlights.

III.Made for hardware builders.

Explore interfaces, compile the RTL and find a starting point for your next design.

02 /AT THE ANVIL

Build, check, and refine.

A little spark. Try the hammer.

THE BLUEPRINT

Start with a clear specification.

Turn an idea into concrete interfaces, behavior and product goals.

01 / DRAW THE BLUEPRINT

THE DESIGN

Shape the hardware.

Build practical RTL components with clear configuration and integration boundaries.

02 / SHAPE THE MATERIAL

THE RESULTS

Check real behavior.

Exercise data transfers, stalls, resets and corner cases across supported configurations.

03 / CHECK THE WORK

THE RELEASE

Share the finished design.

Publish accepted RTL with concise product information and clearly scoped results.

04 / REFINE & CONTINUE

An illustration of hardware craftsmanship. Explore the released RTL and product highlights in the public gallery.

03 /SELECTED WORK

Hardware from the forge.Explore the results.

New designs join these shelves as they are released, with open RTL and scoped results. The ACE projects below are separate research efforts.

RTL / 01

Multi-channel DMAQueued, buffered 32-bit transfers.7 modules · 945 RTL lines9 regression configurationsDefault-configuration generic synthesis

 RTL / 02

Packet routerStore-and-forward, concurrent outputs.7 modules · 681 RTL lines17 configurations · 51 randomized simulations110,088 simulation cyclesDefault-configuration generic synthesis

 RTL / 03

Memory fabricMulti-client arbitration, ordered responses.8 modules · 624 RTL lines27 randomized simulations · 8 endpoint checks6,624 measured transactionsDefault-configuration generic synthesis

 RTL / 04

Fixed-point stream processorInterleaved three-tap processing, frame-stable settings.6 modules · 519 RTL lines27 randomized simulations · 56,945 cycles18,585 valid outputs after the final resetDefault-configuration generic synthesis

 RTL / 05

Credit-aware deficit schedulerByte-cost round robin with per-queue outstanding limits.1 module · 348 RTL lines15 randomized simulations · 145,884 cycles5,544 completions after the final resetDefault-configuration generic synthesis

 RTL / 06

Tagged completion and reorderOut-of-order completions, retired in each client's request order.5 modules · 577 RTL lines15 randomized simulations · 320 legal parameter compilations15,658 retirements after the final resetGeneric synthesis · structural and no-latch checks

 RTL / 07

Banked SECDED scratchpadSingle-bit correction, double-bit detection and background scrubbing.7 modules · 757 RTL lines15 randomized simulations · 96,238 cycles19,526 client transactions after the final resetPer default run: 39 single-bit faults · 741 double-bit pairsGeneric synthesis · connected state, no latches

 RTL / 08

Streaming bilinear image scaler8-bit grayscale up/downscaling with two-row storage.5 modules · 681 RTL lines15 randomized simulations · 69,790 cyclesAfter the final reset: 252 complete valid frames · 8,520 pixelsDefault-configuration generic synthesis

 RTL / 09

Streaming LZ4 block decoderRaw LZ4 blocks with overlapping copies and bounded history.1 module · 384 RTL lines6 configurations · 18 randomized simulations1,086 valid blocks · 85,275 decoded bytesByte-for-byte cross-check with liblz4 1.9.4Default-configuration generic synthesis

Counts cover module definitions and RTL lines, excluding blank lines, comments and test code. All released designs passed scoped RTL engineering acceptance. Default-configuration generic synthesis is listed where completed. The tested configurations do not cover every supported parameter combination; physical signoff and silicon measurements remain outside this scope.

ACE-2 / W4A8PERSISTENT STATE
ACE-2 concept: integer inference with retained K/V across conversation turns NEXT TURNINT8 ACE-2W4 · A8 DECODETOKEN RETAIN K/V24 LAYERS NO REPLAYBETWEEN TURNS
Carry K/V state into the next turn.01 / ACE

THE INTEGER LINE

ACE-2

Keep the conversation going.

A W4A8 accelerator project for Qwen2.5-0.5B, covering numerical reference, synthesizable SystemVerilog, runtime integration, and persistent K/V state.

W4A824 K/V LAYERSRTL
Engineering results

The accepted two-turn test retains all 24 K/V layers and generates four tokens per turn. Integer, logit, and token comparisons show zero mismatches, with no prefix recomputation or software fallback.

The September 26 three-turn diagnostic still awaits final qualification. The results cited here cover RTL simulation and host/oracle comparisons; FPGA and silicon measurements are outside their scope.

Read the test record
View ACE-2
ACE-3 MP / W4A16MIXED PRECISION
ACE-3 concept: G128 packed INT4 weights, FP16 activations and projection output INT4G128FP16ACTIVATIONSPROJECTIONROUND ONCE
INT4 weights, FP16 activations.02 / ACE

THE MIXED-PRECISION LINE

ACE-3 MP

Checking mixed-precision computation.

An independent architecture for native AWQ W4A16 inference, using G128 INT4 weights and FP16 activations. Verification targets projection and attention datapaths at bit level.

AWQ W4A16G128FP16
Engineering results

G128 primitives and a full-input sequential projection engine have passed acceptance. QKV, RoPE, cache, and attention have scoped RTL-simulation results. Complete-model acceptance is still pending.

October 12 source updates add FP16/QKV fixes, file-open checks, a decoder failure probe, and caller integration for input-bound checkpoints. These are source-level changes; V1 full-regression, full-model, and hardware acceptance remain pending.

See verification status
View ACE-3

The diagrams illustrate architecture concepts, without live execution or physical chip layouts. ACE-2 and ACE-3 have their own independent research records; those results do not establish autonomous completion by Vulcan. The cited RTL checks do not constitute hardware signoff.

04 /MATERIALS & TOOLS

From accelerators to other hardware projects.

THE TOOL WALL
Pick the tools that suit the material.

EIGHT DOMAINS / YOUR PROJECT'S TOOLS

  • Chip design
  • FPGA
  • Digital circuits
  • PCB
  • Analog / mixed signal
  • RF
  • Power electronics
  • Package design

SELECT TOOLS FOR THE TASK.

Each domain profile provides relevant knowledge and checks. The project's environment determines which tools and verification steps are available.

05 /YOUR TURN AT THE ANVIL

Bring an idea.Explore what is possible.

Choose a design and explore its interfaces and results. Try compiling the FIFO below with Icarus Verilog.

Open the design gallery
OPEN RTL COLLECTION
git clone https://github.com/aHappend/vulcan-showcase.git
cd vulcan-showcase/projects/ready-valid-fifo
iverilog -g2012 -s rv_fifo -t null rtl/rv_fifo.sv

GIT · ICARUS VERILOG · COMPILE THE RELEASED DESIGN

EXPLORE. INTEGRATE. BUILD.